Espressif Systems /ESP32-S2 /EXTMEM /CACHE_DBG_STATUS1

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Interpret as CACHE_DBG_STATUS1

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DBUS0_ACS_MSK_DCACHE_ST)DBUS0_ACS_MSK_DCACHE_ST 0 (DBUS1_ACS_MSK_DCACHE_ST)DBUS1_ACS_MSK_DCACHE_ST 0 (DBUS2_ACS_MSK_DCACHE_ST)DBUS2_ACS_MSK_DCACHE_ST 0 (DBUS0_ACS_CNT_OVF_ST)DBUS0_ACS_CNT_OVF_ST 0 (DBUS1_ACS_CNT_OVF_ST)DBUS1_ACS_CNT_OVF_ST 0 (DBUS2_ACS_CNT_OVF_ST)DBUS2_ACS_CNT_OVF_ST 0 (DBUS0_ACS_MISS_CNT_OVF_ST)DBUS0_ACS_MISS_CNT_OVF_ST 0 (DBUS1_ACS_MISS_CNT_OVF_ST)DBUS1_ACS_MISS_CNT_OVF_ST 0 (DBUS2_ACS_MISS_CNT_OVF_ST)DBUS2_ACS_MISS_CNT_OVF_ST 0 (DBUS0_ACS_WB_CNT_OVF_ST)DBUS0_ACS_WB_CNT_OVF_ST 0 (DBUS1_ACS_WB_CNT_OVF_ST)DBUS1_ACS_WB_CNT_OVF_ST 0 (DBUS2_ACS_WB_CNT_OVF_ST)DBUS2_ACS_WB_CNT_OVF_ST 0 (DBUS0_ABANDON_CNT_OVF_ST)DBUS0_ABANDON_CNT_OVF_ST 0 (DBUS1_ABANDON_CNT_OVF_ST)DBUS1_ABANDON_CNT_OVF_ST 0 (DBUS2_ABANDON_CNT_OVF_ST)DBUS2_ABANDON_CNT_OVF_ST 0 (DC_PRELOAD_MISS_CNT_OVF_ST)DC_PRELOAD_MISS_CNT_OVF_ST 0 (DC_PRELOAD_EVICT_CNT_OVF_ST)DC_PRELOAD_EVICT_CNT_OVF_ST 0 (DC_PRELOAD_CNT_OVF_ST)DC_PRELOAD_CNT_OVF_ST 0 (DC_SYNC_SIZE_FAULT_ST)DC_SYNC_SIZE_FAULT_ST 0 (DC_PRELOAD_SIZE_FAULT_ST)DC_PRELOAD_SIZE_FAULT_ST 0 (DCACHE_WRITE_FLASH_ST)DCACHE_WRITE_FLASH_ST 0 (DCACHE_REJECT_ST)DCACHE_REJECT_ST 0 (DCACHE_SET_PRELOAD_ILG_ST)DCACHE_SET_PRELOAD_ILG_ST 0 (DCACHE_SET_SYNC_ILG_ST)DCACHE_SET_SYNC_ILG_ST 0 (DCACHE_SET_LOCK_ILG_ST)DCACHE_SET_LOCK_ILG_ST 0 (MMU_ENTRY_FAULT_ST)MMU_ENTRY_FAULT_ST

Description

register description

Fields

DBUS0_ACS_MSK_DCACHE_ST

The bit is used to indicate interrupt by cpu access dcache while the dbus0 is disabled or dcache is disabled which include speculative access.

DBUS1_ACS_MSK_DCACHE_ST

The bit is used to indicate interrupt by cpu access dcache while the dbus1 is disabled or dcache is disabled which include speculative access.

DBUS2_ACS_MSK_DCACHE_ST

The bit is used to indicate interrupt by cpu access dcache while the dbus2 is disabled or dcache is disabled which include speculative access.

DBUS0_ACS_CNT_OVF_ST

The bit is used to indicate interrupt by dbus0 counter overflow.

DBUS1_ACS_CNT_OVF_ST

The bit is used to indicate interrupt by dbus1 counter overflow.

DBUS2_ACS_CNT_OVF_ST

The bit is used to indicate interrupt by dbus2 counter overflow.

DBUS0_ACS_MISS_CNT_OVF_ST

The bit is used to indicate interrupt by dbus0 miss counter overflow.

DBUS1_ACS_MISS_CNT_OVF_ST

The bit is used to indicate interrupt by dbus1 miss counter overflow.

DBUS2_ACS_MISS_CNT_OVF_ST

The bit is used to indicate interrupt by dbus2 miss counter overflow.

DBUS0_ACS_WB_CNT_OVF_ST

The bit is used to indicate interrupt by dbus0 eviction counter overflow.

DBUS1_ACS_WB_CNT_OVF_ST

The bit is used to indicate interrupt by dbus1 eviction counter overflow.

DBUS2_ACS_WB_CNT_OVF_ST

The bit is used to indicate interrupt by dbus2 eviction counter overflow.

DBUS0_ABANDON_CNT_OVF_ST

The bit is used to indicate interrupt by dbus0 abandon counter overflow.

DBUS1_ABANDON_CNT_OVF_ST

The bit is used to indicate interrupt by dbus1 abandon counter overflow.

DBUS2_ABANDON_CNT_OVF_ST

The bit is used to indicate interrupt by dbus2 abandon counter overflow.

DC_PRELOAD_MISS_CNT_OVF_ST

The bit is used to indicate interrupt by pre-load miss counter overflow.

DC_PRELOAD_EVICT_CNT_OVF_ST

The bit is used to indicate interrupt by pre-load eviction counter overflow.

DC_PRELOAD_CNT_OVF_ST

The bit is used to indicate interrupt by pre-load counter overflow.

DC_SYNC_SIZE_FAULT_ST

The bit is used to indicate interrupt by manual sync configurations fault.

DC_PRELOAD_SIZE_FAULT_ST

The bit is used to indicate interrupt by manual pre-load configurations fault.

DCACHE_WRITE_FLASH_ST

The bit is used to indicate interrupt by dcache trying to write flash.

DCACHE_REJECT_ST

The bit is used to indicate interrupt by authentication fail.

DCACHE_SET_PRELOAD_ILG_ST

The bit is used to indicate interrupt by illegal writing preload registers of icache while icache is busy to issue lock,sync and pre-load operations.

DCACHE_SET_SYNC_ILG_ST

The bit is used to indicate interrupt by illegal writing sync registers of icache while icache is busy to issue lock,sync and pre-load operations.

DCACHE_SET_LOCK_ILG_ST

The bit is used to indicate interrupt by illegal writing lock registers of icache while icache is busy to issue lock,sync or pre-load operations.

MMU_ENTRY_FAULT_ST

The bit is used to indicate interrupt by mmu entry fault.

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